Microelectronic assemblies generally include one or more ICs, such as for example one or more packaged dies (“chips”) or one or more dies. One or more of such ICs may be mounted on a circuit platform, such as a wafer such as in wafer-level-packaging (“WLP”), printed board (“PB”), a printed wiring board (“PWB”), a printed circuit board (“PCB”), a printed wiring assembly (“PWA”), a printed circuit assembly (“PCA”), a package substrate, an interposer, or a chip carrier. Additionally, one IC may be mounted on another IC. An interposer may be an IC, and an interposer may be a passive or an active IC, where the latter includes one or more active devices, such as transistors for example, and the former does not include any active device. Furthermore, an interposer may be formed like a PWB, namely without any circuit elements such as capacitors, resistors, or active devices. Additionally, an interposer includes at least one through-substrate-via.
An IC may include conductive elements, such as pathways, traces, tracks, vias, contacts, pads such as contact pads and bond pads, plugs, nodes, or terminals for example, that may be used for making electrical interconnections with a circuit platform. These arrangements may facilitate electrical connections used to provide functionality of ICs. An IC may be coupled to a circuit platform by bonding, such as bonding traces or terminals, for example, of such circuit platform to bond pads or exposed ends of pins or posts or the like of an IC. Additionally, a redistribution layer (“RDL”) may be part of an IC to facilitate a flip-chip configuration, die stacking, or more convenient or accessible position of bond pads for example.
Conventionally, after an etch back for a backside reveal of through-silicon vias (“TSVs”), a conformal dielectric coating is deposited on the surfaces of the substrate and the revealed TSVs. This is followed by planarization to expose conductor vias of the TSVs and to planarize the backside. After which, a metal layer may be deposited for interconnection with the conductor vias. However, this conventional approach may have yield issues and/or cost issues, which make using it less desirable. Furthermore, this conventional approach may not be suitable for individual interconnections.
Accordingly, it would be desirable and useful to provide for post processing after a backside TSV reveal that improves yield, reduces cost, and/or increases versatility for individual interconnections.